In recent years, a reduction in the cost of color display devices has been achieved. Accompanying the cost reduction, the cost of LCD (Liquid Crystal Display) source drivers has reduced to almost a third during these ten years, and a demand for further cost reduction has been increasing. In order to satisfy the demand as described above, reduction in a chip size of an LSI of the LCD source driver is planned in research, product design, and the like. It is because the most effective means for the cost reduction is the chip size reduction.
The number of gray scales has been increased, and a transition is made from display of 260 thousand colors with six bits for each of RGB to display of 16700 thousand colors with eight bits for each of RGB, for example. Further, a product that displays one billion colors with ten bits for each of RGB has been on the market. For this reason, high accuracy of output buffer amplifiers in the LCD source driver, each of which is composed by a differential amplifier, is demanded.
When an output deviation of the LCD source driver exceeds 10 mV, the deviation is recognized by a human eye and appears as a display defect such as a vertical streak. As described above, it is necessary to cope with two contradictory demands for cost reduction and high accuracy.
A configuration of differential amplifiers that occupy a lot in the area of the LCD source driver LSI greatly influences the cost reduction and the high accuracy. A typical LCD source driver will be described below.
FIG. 1 is a diagram showing a typical configuration of a conventional LCD source driver (also referred to as a “data driver”). Referring to FIG. 1, this LCD source driver is constituted from a data register 1 that samples signals R, G, and B each being a six-bit digital display signal, a latch circuit 2 that latches six-bit digital signals in synchronization with a strobe signal ST, a D/A converter 3 constituted from N parallel stages of digital/analog converters, a liquid crystal gray scale voltage generation circuit 4 that has a gamma-conversion characteristic adjusted to liquid crystal characteristics, and N voltage followers 5 that perform buffering of voltages from the D/A converter 3, respectively.
An LCD panel is provided for intersections between data lines and scan lines, and is constituted from thin-film transistors TFTs (Thin Film Transistors) 6 and pixel capacitances 7. Gates of the TFTs 6 are connected to the scan lines, respectively, and sources of the TFTs 6 are connected to the data lines, respectively. One ends of the pixel capacitances 7 are connected to drains of the TFTs, and the other ends of the pixel capacitances 7 are connected to a COM terminal.
FIG. 1 schematically shows a configuration of one row on the LCD panel (on which a plurality (M) of rows each constituted from N thin-film transistors (TFTs) are provided).
An LCD gate driver not shown sequentially drives gates of the TFTs in respective lines.
The D/A converter 3 performs D/A conversion of the six-bit digital display signals from the latch circuit 2 and supplies the resulting signals to N voltage followers 5-1 to 5-n, respectively, for application to liquid crystals that serve as pixel capacitances 7-1 to 7-N through TFTs 6-1 to 6-N, respectively.
Reference voltages are generated by the liquid crystal gray scale voltage generation circuit 4, and reference voltage selection is performed by a decoder constituted from a ROM switch or the like in the D/A converter 3.
The liquid crystal gray scale voltage generation circuit 4 has a resistor ladder circuit, for example. The resistor ladder circuit is driven by the voltage followers in order to reduce impedance at each reference voltage point or to make fine adjustment of the reference voltages.
As a circuit of each of the N voltage followers 5-1 to 5-N, an operational amplifier circuit having a circuit configuration as shown in FIG. 2, for example, is employed. FIG. 2 is a diagram showing the configuration of a differential amplifier disclosed in Patent Document 1. This differential amplifier is a so-called rail-to-rail amplifier, and is described in a text book or well known literature on CMOS analog circuits as a reference circuit.
Referring to FIG. 2, a differential stage includes a differential pair (MN1, MN2) of N-channel MOS transistors and a differential pair (MP1, MP2) of P-channel MOS transistors in order to achieve a rail-to-rail operation. Outputs of the differential pair (MN1, MN2) are connected to points A and B, respectively, and outputs of the differential pair (MP1, MP2) are connected to points C and D, respectively, in order to add currents of the outputs of the differential pairs (MN1, MN2) and (MP1, MP2). The points A, B, C, and D are the points in a so called folded-cascode connections. In a range where the differential pair (MP1, MP2) does not operate, the differential pair (MN1, MN2) operates, while, in a range where the differential pair (MN1, MN2) does not operate, the differential pair (MP1, MP2) operates. The differential stage that operates over an input range of all supply voltages can be thereby obtained. With regard to an operation of the circuit in FIG. 2, Patent Document 1, Patent Document 2, and the like is referred to. The circuit in FIG. 2 will be further described below.
Referring to FIG. 2, the circuit configuration of this differential amplifier is broadly divided into three: an input (initial) stage 210, an intermediate stage 220, and a final stage 230.
The input stage 210 is constituted from the two differential pairs (MN1, MN2) and (MP1, MP2). Sources of the N-channel MOS transistors MN1 and MN2 are coupled in common to constitute a first differential pair (also referred to as an “N-channel differential pair”). An N-channel MOS transistor MN10 is connected between the first differential pair and a negative power supply (low-potential power supply) VSS2. The N-channel MOS transistor MN10 has a source connected to the negative power supply VSS2, a drain connected to the commonly coupled sources of the N-channel MOS transistors MN1 and MN2, and a gate connected to a constant voltage source terminal BN1 and serves as a constant current source. Sources of the P-channel MOS transistors MP1 and MP2 are coupled in common to constitute a second differential pair (also referred to as a “P-channel differential pair”). A P-channel MOS transistor MP10 is connected between the second differential pair and a positive power supply (high-potential power supply) VDD2. The P-channel MOS transistor MP10 has a source connected to the positive power supply VDD2, a drain connected to the commonly coupled sources of the P-channel MOS transistors MP1 and MP2, and a gate connected to a constant voltage source terminal BP1, and serves as a constant current source. Gates of the P-channel MOS transistor MP1 and the N-channel MOS transistor MN1 are connected in common to an input terminal INN. Gates of the P-channel MOS transistor MP2 and the N-channel MOS transistor MN2 are connected in common to an input terminal INP.
The intermediate stage 220 is the intermediate stage for folded-cascode configuration and includes two floating constant current sources (MN7/MP7 and MN8/MP8).
A drain of the N-channel MOS transistor MN1 of the first differential pair of the input stage 210 is connected to the connection node A between a drain of a P-channel MOS transistor MP3 and a source of a P-channel MOS transistor MP5, in the intermediate stage 220. A drain of the N-channel MOS transistor MN2 is connected to the connecting node B between a drain of a P-channel MOS transistor MP4 and a source of a P-channel MOS transistor MP6, in the intermediate stage 220. A drain of the P-channel MOS transistor MP1 of the second differential pair of the input stage 210 is connected to the connection node C between a drain of an N-channel MOS transistor MN3 and a source of an N-channel MOS transistor MN5, in the intermediate stage 220. A drain of the P-channel MOS transistor MP2 is connected to the connecting node D between a drain of an N-channel MOS transistor MN4 and a source of an N-channel MOS transistor MN6, in the intermediate stage 220.
The P-channel MOS transistors MP3 and MP4 have their drains connected to the nodes A and B, respectively, their sources connected in common to the positive power supply VDD2, and their gates coupled in common.
The P-channel MOS transistor MP5 has a source connected to the node A, and a drain connected to the commonly coupled drains of the P-channel MOS transistors MP3 and MP4, a source of the P-channel MOS transistor MP7, and a drain of the N-channel MOS transistor MN7. The P-channel MOS transistor MP6 has a source connected to the node B, and a drain connected to a source of the P-channel MOS transistor MP8, a drain of the N-channel MOS transistor MN8, and a gate of a P-channel MOS transistor MP9 in the final stage 230. Gates of the P-channel MOS transistors MP5 and MP6 are connected in common to a constant voltage source terminal BP2.
Sources of the N-channel MOS transistors MN3 and MN4 are coupled, while gates of the N-channel MOS transistors MN3 and MN4 are coupled. The commonly coupled sources of the N-channel MOS transistors MN3 and MN4 are connected to the negative power supply VSS2. The drains of the N-channel MOS transistors MN3 and MN4 are connected to the node C and the node D, respectively. The N-channel MOS transistor MN5 has a source connected to the node C, and a drain connected to the commonly coupled gates of the N-channel MOS transistors MN3 and MN4, a source of the N-channel MOS transistor MN7, and a drain of the P-channel MOS transistor MP7. The N-channel MOS transistor NN6 has a source connected to the node D, and a drain connected to a source of the N-channel MOS transistor MN8, a drain of the P-channel MOS transistor MP8, and a gate of an N-channel MOS transistor MN9. Gates of the N-channel MOS transistors MN5 and MN6 are connected in common to a constant voltage source terminal BN2.
The P-channel MOS transistor MP7 has a gate connected to a constant voltage source terminal BP3, a source of the P-channel MOS transistor MP7 connected to the drain of the P-channel MOS transistor MP5, and a drain of the P-channel MOS transistor MP7 connected to the drain of the N-channel MOS transistor MN5.
The N-channel MOS transistor MN7 has a gate connected to a constant voltage source terminal BN3, a source connected to the drain of the N-channel MOS transistor MN5, and a drain connected to the drain of the P-channel MOS transistor MP5. The P-channel MOS transistor MP7 and the N-channel MOS transistor MN7 serve as a floating constant current source.
The P-channel MOS transistor MP8 has a gate connected to a constant voltage source terminal BP4, a source connected to the drain of the P-channel MOS transistor MP6, and a drain connected to the drain of the N-channel MOS transistor MN6.
The N-channel MOS transistor MN8 has a gate connected to a constant voltage source terminal BN4, source connected to the drain of the N-channel MOS transistor MN6, and a drain connected to the drain of the P-channel MOS transistor MP6.
The P-channel MOS transistor MP8 and the N-channel MOS transistor MN8 serve as a floating constant current source.
The final stage 230 is a class-AB output stage controlled by bias voltages BP4 and BN4, and the N-channel MOS transistor MN8/the P-channel MOS transistor MP8.
The P-channel MOS transistor MP9 is an output transistor that has a source connected to the positive power supply VDD2, a gate connected to the source of the P-channel MOS transistor MP8, and a drain connected to an output terminal OUT.
The N-channel MOS transistor MN9 is an output transistor that has a source connected to the negative power supply VSS2, a gate connected to the source of the N-channel MOS transistor MN8, and a drain connected to the output terminal OUT.
One end of a phase compensating capacitor C1 is connected to the node B, while the other end of the phase compensating capacitor C1 is connected to the output terminal OUT. One end of a phase compensating capacitor C2 is connected to the node D, while the other end of the phase compensating capacitor C2 is connected to the output terminal OUT.
In order to realize the rail-to-rail operation, the input stage 210 includes the differential pairs (MP1, MP2) and (MN1, MN2) of mutually opposite conductivity types, and is configured to be of a folded-cascode type. The intermediate stage 220 adds currents of outputs of the P-channel differential pair and the N-channel differential pair of the input stage 210. The intermediate stage 220 constitutes a constant current source circuit that uses the floating current source (refer to Patent Document 3). The floating current source herein includes the N-channel MOS transistor MN7, the P-channel MOS transistor MP7, and the bias terminals BN3 and BP3 that supply the bias voltages (constant voltages) to the gates of the N-channel MOS transistor MN7 and the P-channel MOS transistor MP7, respectively.
In order to realize output rail-to-rail operation, the final stage 230 constitutes a drain output class-AB amplifier. An idling current of this class-AB amplifier is determined by the floating current source (MP8, MN8) and the bias terminals BN4 and BP4.
When an input voltage is low, only the differential pair (MP1, MP2) operates. Conversely, when the input voltage is high, only the differential pair (MN1, MN2) operates. When the input voltage is of an intermediate value between the high and low input voltages, the differential stages (MP1, MP2) and (MN1, MN2) both operate.
That is, in an operation that uses the input voltage closer to the supply voltage VSS2, only the differential stage (MP1, MP2) operates, and the differential pair (MN1, MN2) does not operate. The reason for this is as follows. An enhancement-type N-channel MOS transistor is generally used and in order for the enhancement-type N-channel MOS transistor to operate, there needs to be a voltage of a transistor threshold voltage (VT)+α present between the gate and source of the N-channel MOS transistor.
When the input voltage is around 0V closer to the supply voltage VSS2 of the negative power supply, or a gate voltage of the input differential transistor is around 0V, a source potential of the input differential transistor also becomes around 0V. Accordingly, it can be seen that the differential pair (MN1, MN2) does not operate. When the input voltage is around the supply voltage VDD2 closer to the supply voltage VDD2 of the positive power supply, or the gate voltage of the input differential transistor is around VDD, the source potential of the input differential transistor also becomes around the supply voltage VDD. Accordingly, it can be seen that the differential pair (MP1, MP2) does not operate. When the input voltage is approximately VTN to VDD−VTP (in which VTN indicates a threshold voltage of an N-channel MOS transistor, and VTP indicates a threshold voltage of a P-channel MOS transistor), both of the differential stages (MP1, MP2) and (MN1, MN2) operate.                [Patent Document 1]        
U.S. Pat. No. 5,311,145                [Patent Document 2]        
JP Patent Kokai Publication No. JP-A-6-326529                [Patent Document 3]        
JP Patent Kokoku Publication No. JP-A-6-91379